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| HD74AC74 Dual D-Type Positive Edge-Triggered Flip-Flop REJ03D0277-0200Z (Previous ADE-205-361 (Z)) Rev.2.00 Jul.16.2004 Description The HD74AC74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. Features Asynchronous Inputs: Low input to SD (Set) sets Q to High level Low input to CD (Clear) sets Q to Low level Clear and Set are independent of clock Simultaneous Low on CD and SD makes both Q and Q High * Outputs Source/Sink 24 mA * Ordering Information Part Name HD74AC74P HD74AC74FPEL HD74AC74RPEL HD74AC74TELL Package Type DIP-14 pin SOP-14 pin (JEITA) SOP-14 pin (JEDEC) TSSOP-14 pin Package Code Package Abbreviation Taping Abbreviation (Quantity) DP-14, -14AV FP-14DAV FP-14DNV TTP-14DV P FP RP T -- EL (2,000 pcs/reel) EL (2,500 pcs/reel) ELL (2,000 pcs/reel) Notes: 1. Please consult the sales office for the above package availability. 2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of the package code. Pin Arrangement CD1 1 D1 2 CP1 3 SD1 4 Q1 5 Q1 6 GND 7 D2 CD2 CP2 SD2 CP1 D1 SD1 CD1 14 VCC 13 CD2 12 D2 11 CP2 10 SD2 9 Q2 8 Q2 Q1 Q1 Q2 Q2 (Top view) Rev.2.00, Jul.16.2004, page 1 of 7 HD74AC74 Logic Symbol D1 SD1 Q1 D2 SD2 Q2 CP1 Q1 CP2 Q2 CD1 CD2 Pin Names D1, D2 CP1, CP2 CD1, CD2 SD1, SD2 Q1, Q1, Q2, Q 2 Data Inputs Clock Pulse Inputs Direct Clear Inputs Direct Set Inputs Outputs Truth Table (Each Half) Inputs SD L H L H H H H L X CD H L L H H H High Voltage Level Low Voltage Level Immaterial Low-to-High Clock Transition Previous Q (Q) before Low-to-High Transition of Clock CP X X X X X X H L X D H L H H L Q0 Outputs Q L H H L H Q0 Q L : : : : Q0 (Q0) : Logic Diagram SD D CP Q Q CD Please note that this diagram is provised only for the understanding of logic operations and should not be used to estimate propagation delays. Rev.2.00, Jul.16.2004, page 2 of 7 HD74AC74 Absolute Maximum Ratings Item Supply voltage DC input diode current DC input voltage DC output diode current DC output voltage DC output source or sink current DC VCC or ground current per output pin Storage temperature Symbol VCC IIK VI IOK VO IO ICC, IGND Tstg Ratings -0.5 to 7 -20 20 -0.5 to Vcc+0.5 -50 50 -0.5 to Vcc+0.5 50 50 -65 to +150 Unit V mA mA V mA mA V mA mA C Condition VI = -0.5V VI = Vcc+0.5V VO = -0.5V VO = Vcc+0.5V Recommended Operating Conditions Item Supply voltage Input and output voltage Operating temperature Input rise and fall time (except Schmitt inputs) VIN 30% to 70% VCC Symbol VCC VI, VO Ta tr, tf Ratings 2 to 6 0 to VCC -40 to +85 8 V V C ns/V VCC = 3.0V VCC = 4.5 V VCC = 5.5 V Unit Condition DC Characteristics Item Symbol VIH Vcc (V) 3.0 4.5 5.5 VIL 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 VOL 5.5 3.0 4.5 5.5 3.0 4.5 Input leakage current Dynamic output current* IIN IOLD IOHD 5.5 5.5 5.5 5.5 min. 2.1 3.15 3.85 -- -- -- 2.9 4.4 5.4 2.58 3.94 4.94 -- -- -- -- -- -- -- -- -- Ta = 25C typ. 1.5 2.25 2.75 1.50 2.25 2.75 2.99 4.49 5.49 -- -- -- 0.002 0.001 0.001 -- -- -- -- -- -- max. -- -- -- 0.9 1.35 1.65 -- -- -- -- -- -- 0.1 0.1 0.1 0.32 0.32 0.32 0.1 -- -- Ta = -40 to +85C min. 2.1 3.15 3.85 -- -- -- 2.9 4.4 5.4 2.48 3.80 4.80 -- -- -- -- -- -- -- 86 -75 -- max. -- -- -- 0.9 1.35 1.65 -- -- -- -- -- -- 0.1 0.1 0.1 0.37 0.37 0.37 1.0 -- -- 40 A mA mA A V VOUT = 0.1 V or VCC -0.1 V Unit Condition Input Voltage V VOUT = 0.1 V or VCC -0.1 V Output voltage VOH VIN = VIL or VIH IOUT = -50 A VIN = VIL or VIH IOH = -12 mA IOH = -24 mA IOH = -24 mA VIN = VIL or VIH IOUT = 50 A VIN = VIL or VIH IOL = 12 mA IOL = 24 mA IOL = 24 mA VIN = VCC or GND VOLD = 1.1 V VOHD = 3.85 V VIN = VCC or ground Quiescent supply 5.5 -- -- 4.0 ICC current *Maximum test duration 2.0 ms, one output loaded at a time. Rev.2.00, Jul.16.2004, page 3 of 7 HD74AC74 AC Characteristics Ta = +25C CL = 50 pF Item Maximum clock frequency Propagation delay CDn or SDn to Qn or Qn Propagation delay CDn or SDn to Qn or Qn Propagation delay CPn to Qn or Qn Propagation delay CPn to Qn or Qn Note: Symbol fmax tPLH tPHL tPLH tPHL VCC (V)*1 Min 3.3 100 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 140 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Typ 125 160 8.0 6.0 10.5 8.0 8.0 6.0 8.0 6.0 Max -- -- 12.0 9.0 12.0 9.5 13.5 10.0 14.0 10.0 Ta = -40C to +85C CL = 50 pF Min 95 125 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 -- -- 13.0 10.0 13.5 10.5 16.0 10.5 14.5 10.5 Max MHz ns ns ns ns Unit 1. Voltage Range 3.3 is 3.3 V 0.3 V Voltage Range 5.0 is 5.0 V 0.5 V AC Operating Requirements Ta = +25C CL = 50 pF Item Set-up time, HIGH or LOW Dn to CPn Hold time, HIGH or LOW Dn to CPn CPn or CDn or SDn Pulse width Recovery time Symbol VCC (V)*1 Typ tsu 3.3 1.5 th tw trec 5.0 3.3 5.0 3.3 5.0 3.3 1.0 -2.0 -1.5 3.0 2.5 -2.5 -2.0 Ta = -40C to +85C CL = 50 pF Unit ns ns ns ns Guaranteed Minimum 4.0 4.5 3.0 0 0 5.5 4.5 0 0 3.0 0 0 7.0 5.0 0 0 5.0 CDn or SDn to CP Note: 1. Voltage Range 3.3 is 3.3 V 0.3 V Voltage Range 5.0 is 5.0 V 0.5 V Capacitance Item Input capacitance Power dissipation capacitance Symbol CIN CPD 4.5 35.0 Typ pF pF Unit VCC = 5.5 V VCC = 5.0 V Condition Rev.2.00, Jul.16.2004, page 4 of 7 HD74AC74 Package Dimensions As of January, 2003 19.20 20.32 Max 14 8 Unit: mm 1 2.39 Max 1.30 7 7.62 6.30 7.40 Max 0.51 Min 2.54 Min 5.06 Max 2.54 0.25 0.48 0.10 0.25 - 0.05 0 - 15 + 0.10 Package Code JEDEC JEITA Mass (reference value) DP-14 Conforms Conforms 0.97 g 19.20 20.32 Max 14 8 Unit: mm 1 2.39 Max 1.30 7 7.62 6.30 7.40 Max 0.51 Min 2.54 Min 5.06 Max 2.54 0.25 *0.48 0.08 *0.25 0.06 0 - 15 *NI/Pd/AU Plating Package Code JEDEC JEITA Mass (reference value) DP-14AV Conforms Conforms 0.97 g Rev.2.00, Jul.16.2004, page 5 of 7 HD74AC74 As of January, 2003 Unit: mm 10.06 10.5 Max 14 8 5.5 1 7 *0.20 0.05 2.20 Max 0.20 7.80 + 0.30 - 1.42 Max 1.15 0 - 8 0.70 0.20 1.27 *0.40 0.06 0.12 M Package Code JEDEC JEITA Mass (reference value) FP-14DAV -- Conforms 0.23 g *Ni/Pd/Au plating 0.10 0.10 0.15 As of January, 2003 Unit: mm 8.65 9.05 Max 14 8 3.95 1 1.75 Max *0.20 0.05 7 6.10 - 0.30 1.08 + 0.10 0.635 Max 0 - 8 0.11 0.14 + 0.04 - 1.27 *0.40 0.06 0.67 0.60 + 0.20 - 0.15 0.25 M Package Code JEDEC JEITA Mass (reference value) FP-14DNV Conforms Conforms 0.13 g *Ni/Pd/Au plating Rev.2.00, Jul.16.2004, page 6 of 7 HD74AC74 As of January, 2003 Unit: mm 5.00 5.30 Max 14 8 4.40 1 7 0.65 1.0 0.13 M 6.40 0.20 0.83 Max *0.15 0.05 *0.20 0.05 1.10 Max 0.10 0.07 +0.03 -0.04 0 - 8 0.50 0.10 *Ni/Pd/Au plating Package Code JEDEC JEITA Mass (reference value) TTP-14DV -- -- 0.05 g Rev.2.00, Jul.16.2004, page 7 of 7 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. 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